1. Field of the Invention
The present invention relates to a transfer gate circuit composed of FETs (Field Effect Transistors) and a dynamic divider circuit using such a transfer gate circuit.
2. Description of the Related Art
The divider circuit is well known in the art of digital circuitry. For example, a PLL synthesizer circuit has included the divider circuit for dividing a frequency of output signal from a quartz oscillator. The divider circuit functions as not only a frequency divider but also a binary counter.
FIG. 3 shows a known dynamic 1/2 divider circuit using transfer gate circuits. This type of 1/2 divider circuit is disclosed in Japanese Patent Publication No. 2-95014 and No. 4-16023.
The 1/2 divider circuit has a source follower circuit 10 which is connected at its output end to an input of a source follower circuit 20 through a transfer gate 31. An output of the source follower circuit 20 is connected to an input of another source follower circuit 10 through an inverter circuit 32 and a transfer gate 33.
The source follower circuit 10 has a D-MESFET (Depletion Mode of Metal Semiconductor FET) 11 a drain D of which is connected to a ground line GND while a source S of which is connected to a power supply line VEE via a level shift diode 12 and a D-MESFET 13. The D-MESFET 13 which gate G is connected to its source S forms a constant-current source. The input and output of the source follower circuit 10 are respectively the gate G and the source S of the D-MESFET 11.
The source follower circuit 20 has the same construction as the source follower circuit 10. Namely, the source follower circuit 20 has a D-MESFET 21 a drain of which is connected to the ground line GND. A source S of the D-MESFET 21 is connected to the power supply line VEE via a level shift diode 22 and a D-MESFET 23. The D-MESFET 23 which gate G is connected to its source S forms a constant-current source. The input and the output of the source follower circuit 20 are respectively the gate G and the source S of the D-MESFET 21.
The 1/2 divider circuit described above operates as shown in FIG. 4A to 4E, in response to a variable-frequency input signal IN supplied to a gate G of the transfer gate 33 and an input signal supplied to a gate G of the transfer gate 31, where *IN is inverse relation to IN in binary logic level.
(1) It is assumed as shown in parentheses in FIG. 3 that, in the initial state of the 1/2 divider circuit, the input signals IN and *IN are high (H) and low (L) levels respectively, while the gate G of the D-MESFET 21 is low level (L). In this state, the transfer gate 31 and 33 are off and on respectively, the D-MESFET 21 is off, the input and output of the inverter circuit 32 are low and high levels respectively, the gate G (IN10) and source of the D-MESFET 11 are high and low level.
(2) Then, the input signal IN and *IN turn to low and high levels respectively, so the transfer gate 33 turns off, the gate G of the D-MESFET 11 is held at high level and the output level of the source follower circuit 10 are held unchanged. While the transfer gate 31 turns on, the gate G (IN20) of the D-MESFET 21 turns to a high level, the output of the D-MESFET 21 turns to high level and the output signal OUT turns to a low level.
(3) Subsequently, the input signals IN and *IN turn to high and low levels respectively, so the transfer gate 31 turns off, the gate G of the D-MESFET 21 is held at a high level and the output of the source follower circuit 20 is held unchanged. Accordingly, the output signal OUT also is held at the low level. While, the transfer gate 33 turns on, the gate G of the D-MESFET 11 turns to a low level and the output of the source follower circuit 10 turns to a low level.
(4) Subsequently, the input signal IN and *IN turn to low and high levels, respectively, so the transfer gate 33 turns off, the gate G of the D-MESFET 11 is held at a low level and the output levels of the source follower circuit 10 is held unchanged. While, the transfer gate 31 turns on, the gate G of the D-MESFET 21 turns to a low level, the output of the source follower circuit 20 turns to a low level and the output signal OUT turns to a high level.
The above-described operation is repeated, the obtaining output signal OUT as the 1/2 frequency division of the input signal IN.
The above-described dynamic 1/2 divider circuit excels in the high speed operation and can operate when the input signal has a high frequency within the range of 3 to 10 GHz.
This divider circuit, on the other hand, suffers from the following disadvantage. When the frequency of the input signal IN is low and the states of the signals are inverse to those shown in the parentheses in FIG. 3, time integration of the leak current, which flows from the input of the source follower circuit 20 to the output of the source follower circuit 10 through the transfer gate 31, grows to a level which is not negligible. Consequently, the levels of the input and the output of the source follower circuit 20 are undesirably inverted to cause erroneous operation of the 1/2 frequency divider circuit.